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| freescale semiconductor data sheet: advance information document number: mcf54418 rev. 6, 09/2010 ? freescale semiconductor, inc., 2010. all rights reserved. preliminary?subject to change without notice this document contains information on a new product. specifications and information herein are subject to change without notice. mcf5441x mapbga?256 17mm x 17mm mapbga?196 12 mm x 12 mm ? version 4 coldfire ? core with emac and mmu ? up to 385 dhrystone 2.1 mips @ 250 mhz ? 8 kbytes instruction cache and 8 kbytes data cache ? 64 kbytes internal sram dual-ported to processor local bus and other crossbar switch masters ? system boot from nor, nand, spi flash, eeprom, or fram ? crossbar switch technology (xbs) for concurrent access to peripherals or ram from multiple bus masters ? 64-channel dma controller ? sdram controller supporting full-speed operation from a single x8 ddr2 component up to 250 mhz ? 32-bit flexbus external memory interface for ram, rom, mram, and programmable logic ? usb 2.0 host controller ? usb 2.0 host/device/on-the-go controller ? 8-bit single data rate ulpi port usable by the dedicated usb host module or the usb host/device/otg module ? dual 10/100 ethernet macs with hardware crc checking/genera tion, ieee 1588-2002 support, and optional ethernet switch ? cpu direct-attached hardware accelerator for des, 3des, aes, md5, sha-1, and sha-256 algorithms ? random number generator ? enhanced secure digital host controller for sd, sdhc, sdio, mmc, and mmcplus cards ? two iso7816 smart card interfaces ?two flexcan modules ?six i 2 c bus interfaces with dma support in master mode ? two synchronous serial interfaces ? four 32-bit timers with dma support ? four programmable interrupt timers ? 8-channel, 16-bit motor control pwm timer ? dual 12-bit adcs with shared input channels and multiple conversion trigger sources ? dual 12-bit dacs with dma support ? 1-wire module with dma support ? nand flash controller ? real-time clock with 32 -khz oscillator, 2 kb standby sram, and battery backup supply input ? up to four dma-supported serial peripheral interfaces (dspi) ? up to ten uarts with single-wire mode support ? up to five external irq interrupts and 2 external dma request/acknowledge pairs ? up to 16 processor local bus rapid gpio pins ? up to 87 standard gpio pins mcf5441 x coldfire ? microprocessor data sheet
mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 2 table of contents 1 mcf5441 x family comparison . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .5 2.1 power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2 supply voltage sequencing . . . . . . . . . . . . . . . . . . . . . . .7 2.2.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . .8 2.2.2 power-down sequence . . . . . . . . . . . . . . . . . . . .8 2.3 power consumption specifications . . . . . . . . . . . . . . . . .8 3 pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .9 3.1 signal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2 pinout?196 mapbga . . . . . . . . . . . . . . . . . . . . . . . . .18 3.3 pinout?256 mapbga . . . . . . . . . . . . . . . . . . . . . . . . .19 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .20 4.2 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .21 4.3 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.4 static latch-up (lu) . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.5 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . .22 4.6 output pad loading and slew rate . . . . . . . . . . . . . . . . .24 4.7 ddr pad drive strengths. . . . . . . . . . . . . . . . . . . . . . . .25 4.8 oscillator and pll electrical characteristics . . . . . . . . .26 4.9 reset timing specifications . . . . . . . . . . . . . . . . . . . . . .27 4.10 flexbus timing specifications . . . . . . . . . . . . . . . . . . . .28 4.11 nand flash controller (nfc) timing specifications . . . .30 4.12 ddr sdram controller timing specifications . . . . . . . .33 4.13 usb transceiver timing specifications . . . . . . . . . . . . . .35 4.14 ulpi timing specifications. . . . . . . . . . . . . . . . . . . . . . .35 4.15 esdhc timing specifications. . . . . . . . . . . . . . . . . . . . .36 4.15.1 esdhc timing specifications . . . . . . . . . . . . . . 37 4.15.2 esdhc electrical dc characteristics . . . . . . . . 38 4.16 sim timing specifications . . . . . . . . . . . . . . . . . . . . . . . 38 4.16.1 general timing requirements . . . . . . . . . . . . . . 39 4.16.2 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . 39 4.16.3 power-down sequence . . . . . . . . . . . . . . . . . . . 40 4.17 ssi timing specifications . . . . . . . . . . . . . . . . . . . . . . . 41 4.18 12-bit adc specifications . . . . . . . . . . . . . . . . . . . . . . 43 4.19 12-bit dac timing specifications . . . . . . . . . . . . . . . . . 44 4.20 mcpwm timing specifications . . . . . . . . . . . . . . . . . . . 45 4.21 i 2 c timing specifications . . . . . . . . . . . . . . . . . . . . . . . 45 4.22 ethernet assembly timing specifications . . . . . . . . . . . 46 4.22.1 receive signal timing specifications. . . . . . . . . 47 4.22.2 transmit signal timing specifications . . . . . . . . 47 4.22.3 asynchronous input si gnal timing specifications48 4.22.4 mdio serial management timing specifications 48 4.23 32-bit timer module timing specif ications. . . . . . . . . . . 49 4.24 dspi timing specifications . . . . . . . . . . . . . . . . . . . . . . 49 4.25 sbf timing specifications . . . . . . . . . . . . . . . . . . . . . . 52 4.26 1-wire timing specifications. . . . . . . . . . . . . . . . . . . . . 53 4.27 general purpose i/o timing spec ifications. . . . . . . . . . 53 4.28 rapid general purpose i/o timi ng specifications . . . . . 53 4.29 jtag and boundary scan timing specifications . . . . . . 54 4.30 debug ac timing specifications . . . . . . . . . . . . . . . . . . 56 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6 product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 3 peripheral bus controller 1 mcpwm gpio 4 i 2 cs 1 wire version 4 coldfire core pll pll adc ? analog-to-digital converter bdm ? background debug module cau ? cryptography acceleration unit dac ? digital-to-analog dspi ? dma serial peripheral interface edma ? enhanced direct memory access module esdhc ? enhanced secure digital host controller emac ? enchance multiply-accumulate unit eport ? edge port module gpio ? general purpose input/output module i 2 c ? inter-intergrated circuit intc ? interrupt controller jtag ? joint test action group interface mcpwm ? motor control pulse width modulator pit ? programmable interrupt timers pll ? phase locked loop module rgpio ? rapid gpio rng ? random number generator rtc ? real time clock ssi ? synchronous serial interface usb otg ? universal serial bus on-the-go controller mcf5441 x jtag crossbar switch (xbs) 64 kb sram rgpio ddr2 controller flexbus usb otg mmu nand flash esdhc edma l2 switch 2 ethernet controller usb host 4 dma smart card peripheral bus controller 0 timers adc rtc & khz rng eport 4 pits 3 intcs 2 flexcans controllers oscillator oscillator 2 ssis 8 kb instruction cache 8 kb data cache 2 dspis 2 dspis 4 uarts 2 i 2 cs 2 dacs serial boot facility emac bdm cau hardware divide 6 uarts note: each of the crossbar switch masters, the flexbus and sdram controller have access to peripheral bus controller 0, which is not shown. mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice mcf5441x family comparison freescale semiconductor 4 1 mcf5441 x family comparison table 1. mcf5441 x family configurations module mcf54410 mcf54415 mcf54416 mcf54417 mcf54418 version 4 coldfire core with emac (enhanced multiply-accumulate unit) and mmu (memory management unit) ????? cryptography acceleration unit (cau) ? ? ? ? ? core (system) and sdram clock up to 250 mhz peripheral clock (core clock ? 2) up to 125 mhz external bus (flexbus) clock up to 100 mhz performance (dhrystone 2.1 mips) up to 385 static ram (sram) 64 kbytes independent data/instruction cache 8 kbytes each usb 2.0 host controller ? ???? usb 2.0 host/device/on-the-go controller ????? utmi+ low pin interface (ulpi) for external high-speed usb phy ? ???? 10/100 mbps ethernet controller with ieee 1588 support 12222 level 2 ieee 1588-compliant 3-port ethernet switch ??? ?? enhanced secure digital host controller (esdhc) ????? smart card/subscriber identity module (sim) ? 2 ports 2 ports 2 ports 2 ports uarts 6 10 10 10 10 dspi 34444 can 2.0b controllers 12222 i 2 c 46666 synchronous serial interface (ssi) 12222 12-bit adc ? ???? 12-bit dac ? 2 2 2 2 32-bit dma timers 44444 periodic interrupt timers (pit) 44444 motor control pwm timer (mcpwm) ? 8 channel 8 channel 8 channel 8 channel 64-channel dma controller ????? real-time clock with 2 kb standby ram and battery back-up input ????? ddr2 sdram controller ????? flexbus external memory controller ????? hardware design considerations mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 5 1.1 ordering information 2 hardware design considerations 2.1 power filtering to further enhance noise isolation, an external filter is strongly recommended for the analog v dd pins (vdda_pll and vdda_dac_adc). the filter shown in figure 1 should be connected between the boa rd 3.3 v (nominal) supply and the analog pins. the resistor and capacitors should be placed as cl ose to the dedicated analog v dd pin as possible. the 10 ? resistor in the given filter is required. nand flash controller ????? 1-wire ? interface ????? serial boot facility ????? watchdog timer ????? interrupt controllers (intc) 33333 edge port module (eport) 3 irqs 5 irqs 5 irqs 5 irqs 5 irqs rapid gpio pins 9 16 16 16 16 general-purpose i/o (gpio) pins 48 87 87 87 87 jtag - ieee ? 1149.1 test access port ????? package 196 mapbga 256 mapbga table 2. orderable part numbers freescale part number description package speed temperature mcf54410cmf250 mcf54410 mi croprocessor 196 mapbga 250 mhz ?40 to +85 ? c mcf54415cmj250 mcf54415 microprocessor 256 mapbga mcf54416cmj250 mcf54416 microprocessor mcf54417cmj250 mcf54417 microprocessor MCF54418CMJ250 mcf54418 microprocessor table 1. mcf5441 x family configurations (continued) module mcf54410 mcf54415 mcf54416 mcf54417 mcf54418 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice hardware design considerations freescale semiconductor 6 figure 1. oscillator/pll/dac power filter figure 2 shows an example for isolating the adc power supply fr om the i/o supply (evdd) and ground. note that in this power supply the 10 ? resistor is replaced by a 0 ? resistor. this will reduce the ir drop into the adc, limiting additional gain error. figure 2. adc power filter figure 3 shows an example for bypassing the internal core digital power supply for the mpu. this bypass should be applied to as many ivdd signals as routing allows. each one s hould be placed as close to the ball as possible. figure 3. ivdd power filter figure 4 shows an example for bypassing the external pad ring digital power supply for the mpu. this bypass should be applied to as many evdd signals as routing allows. each on e should be placed as close to the ball as possible. figure 4. evdd power filter vdd_osc_a_pll 10 ? 0.1 f evdd pin 1 f gnd vss_osc 100 mhz board 3.3 v 0 ? 0.1 f vdda_adc 10 f gnd supply board 1.2 v 0.1 f ivdd 1 f gnd supply board 3.3 v 0.1 f evdd 1 f gnd supply hardware design considerations mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 7 figure 5 shows an example for bypassing the flexbus power supply for the mpu. this bypass should be applied to as many fb_vdd signals as routing allows . each one should be placed as close to the ball as possible. figure 5. fb_vdd power filter 2.2 supply voltage sequencing figure 6 shows requirements in the sequencing of the i/o v dd (ev dd ), flexbus v dd (fbv dd ), sdram v dd (sdv dd ), pll v dd (vdd_osc_a_pll), and internal logic/core v dd (iv dd ). figure 6. supply voltage sequencing and separation cautions the relationships between fbv dd , sdv dd and ev dd are non-critical during power-up and power-down sequences. fbv dd (1.8 ? 3.3v), sdv dd (2.5v or 1.8v) and ev dd are specified relative to iv dd . note all i/o vdd pins must be powered on when the device is functioning, except when in standby mode. in standby mode, all i/o vdd pins, except vstby_rtc (battery), can be switched off. board 1.8?3.3 v 0.1 f fb_vdd 1 f gnd supply ev dd /fbv dd (3.3v) iv dd , vdd_osc_a_pll time 3.3v 1.5v 0 dc power supply voltage notes: 1 input voltage must not be great er than the supply voltage (ev dd , fbv dd , sdv dd , iv dd , or pv dd ) by more than 0.5v at any time, including during power-up. 2 use 25 v/millisecond or slower rise time for all supplies. 2.5v sdv dd (2.5v ? ddr) 1.8v sdv dd /fbv dd (1.8v ? ddr2) supplies stable mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice hardware design considerations freescale semiconductor 8 2.2.1 power-up sequence if ev dd /fbv dd /sdv dd are powered up with the iv dd at 0 v, the sense circuits in the i/ o pads cause all pad output drivers connected to the ev dd /fbv dd /sdv dd to be in a high impedance state. there is no limit on how long after ev dd /fbv dd /sdv dd powers up before iv dd must power up. iv dd should not lead the ev dd , fbv dd , or sdv dd by more than 0.4 v during power ramp-up, or there will be high curren t in the internal esd protection diodes. the rise times on the power supplies should be slower than 25 v/millisecond to avoid turning on the internal esd protection clamp diodes. 2.2.2 power-down sequence if iv dd /pv dd are powered down first, sense circuits in the i/o pads cause all output driv ers to be in a high impedance state. there is no limit on how long after iv dd and pv dd power down before ev dd , fbv dd , or sdv dd must power down. iv dd should not lag ev dd , fbv dd , or sdv dd going low by more than 0.4 v during power down or there will be undesired high current in the esd protection diodes. there are no re quirements for the fall times of the power supplies. the recommended power down sequence is as follows: 1. drop iv dd /pv dd to 0 v. 2. drop ev dd /fbv dd /sdv dd supplies. 2.3 power consumption specifications table 3. estimated power consumption specifications characteristic symbol typical unit core operating supply current (nominal 1.2 v) 1 run mode wait mode doze mode stop00 mode stop01 mode stop02 mode stop03 mode ivdd 127 33 32 9.3 9.2 3.6 3.4 ma flexbus operating supply current run mode (application dependent) wait mode doze mode stop00 mode stop01, stop02, stop03 mode fbvdd 80 49 42 40 28 ma sdram operating supply current (ddr2 at 1.8 v) isys(dq) [ ? 8, 2 ? dqs] isys(wr) [ ? 8, 2 ? dqs] isys(rd) [ ? 8, 2 ? dqs] sdram input reference current isys(ref) sdram termination current isys(termrd) total sdidd mpu side 2 sdvdd sdvref sdvtt 3 15 15 1.3 41 75 ma oscillator/pll operating supply current (nominal 3.3 v) run, wait, doze, stop00, stop01 mode stop02 mode stop03 mode vdd_osc_a_pll 10 6 1 ma pin assignments and reset states mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 9 3 pin assignments and reset states 3.1 signal multiplexing the following table lists all the mcf5441 x pins grouped by function. the dir column is the direction for the primary function of the pin only. refer to the following sections for packag e diagrams. for a more detailed discussion of the mcf5441 x signals, consult the mcf5441x reference manual (mcf54418rm). note in this table and throughout this document a single signal within a group is designated without square brackets (i.e., fb_ad23), while designations for multiple signals within a group use brackets (i.e., fb_ad[23:21]) and is meant to include all signals within the two bracketed numbers when these num bers are separated by a colon. note the primary functionality of a pin is not necessarily its default functionality. most pins that are muxed with gpio default to their gpio functionality. see table 4 for a list of the exceptions. external i/o pad operating supply current (nominal 3.3 v) evdd ? 3 ma usb operating supply current (nominal 3.3 v) vdd_usbo, vdd_usbh 30 ma adc operating supply current (nominal 3.3 v) speed mode 00 speed mode 01 vdda_adc 14 22 ma dac operating supply current (nominal 3.3 v) vdda_dac_adc 11 ma rtc standby supply current istby vstby_rtc 17 ? a 1 current measured at maximum system clock freque ncy, all modules active, and default drive strength with matching load. 2 ddr2 interface power is estimated from the mi cron ddr2 data sheet. the numbers given in this table do not include the actual power consumption of the memory itself. the current drawn by the memory needs to be added to the values in this table and may be several hundred ma. 3 evdd values depend on the application, with the restrictions that any single pin cannot exceed 25 ma and that the total power does not exceed the thermal characteristics. table 3. estimated power consumption specifications (continued) characteristic symbol typical unit mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice pin assignments and reset states freescale semiconductor 10 table 4. special-case default signal functionality pin default signal fb_clk, fb_oe , fb_r/w , fb_be/bwe [1:0], fb_cs [5:4] fb_clk, fb_oe , fb_r/w , fb_be/bwe [1:0], fb_cs [5:4] fb_ale fb_ale or fb_ts (depending on rcon[3]) fb_be/bwe3 boot from nfc, nf_ale. otherwise, fb_be/bwe3 . fb_be/bwe2 boot from nfc, nf_cle. otherwise, fb_be/bwe2 . fb_cs1 boot from nfc, nfc_ce. otherwise, gpio. fb_cs0 boot from flexbus, fb_cs0. otherwise, gpio. fb_ta boot from nfc, nfc_r/b . otherwise, fb_ta . allpst, pst[3:0], ddata[3:0] allpst, pst[3:0], ddata[3:0] table 5. mcf5441 x signal information and muxing signal name gpio alternate 1 alternate 2 pullup (u) 1 pulldown (d) direction 2 voltage domain pad type 3 196 mapbga 4 256 mapbga reset reset ? ? ? u ievddssr k14 k15 rstout ?? ?? oevddmsr l13 l16 clock extal/ rmii_ref_clk ?? ?? i 5 evdd ae g14 g16 xtal ? ? ? ? oevdd ae h14 h16 mode selection bootmod[1:0] ? ? ? ? i evdd msr g5,h5 k5, l5 flexbus fb_ad[31:24]/ nfc_io[15:8] 6 ?? ?? i/o fbvdd fsr a10, a9, b9, c9, a8, b8, c8, a7 b9, c8, a9, b8, d8, a8, d7, b7 fb_ad[23:16]/ nfc_io[7:0] 6 ?? ?? i/o fbvdd fsr b7, c7, c6, b6, a6, a5, b5, a4 c7, a7, d6, a6, b6, d5, c6, a5 pin assignments and reset states mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 11 fb_ad[15:10] ? ? ? ? 7 i/o fbvdd fsr c5, a3, b4, c4, b3, a2 b5, a4, a3, d4, b4, c5 fb_ad[9:8] ? ? ? u 8 i/o fbvdd fsr b2, c3 c4, b3 fb_ad[7:0] ? ? ? ? i/o fbvdd fsr d4, b1, c2, d3, c1, d2, e3, d1 c3, e4, d3, e3, a2, b2, c2, f3 fb_ale pa7 fb_ts ??o fbvdd fsr e2 d2 fb_oe / nfc_re pa6 fb_tbst / nfc_re ?? ofbvdd fsr h1 f1 fb_r/w / nfc_we pa 5 ? ? ? ofbvdd fsr h2 g2 fb_ta pa4 ? nfc_r/b u 9 ofbvdd fsr h3 h3 fb_be/bwe3 pa 3 f b _ c s 3 fb_a1/ nfc_ale 10 ? ofbvdd fsr f3 c1 fb_be/bwe2 pa 2 f b _ c s 2 fb_a0/ nfc_cle 11 ?o fbvdd fsr e1 e2 fb_be/bwe [1:0] pa[1:0] fb_tsiz[1:0] ? ? o fbvdd fsr f2, f1 d1, f4 fb_clk pb7 ? ? ? ofbvdd fsr g1 g1 fb_cs5 pb6 dack1 ?? ofbvdd fsr ? f2 fb_cs4 pb5 dreq1 ?? ofbvdd fsr ? b1 fb_cs1 pb4 ? nfc_ce ? ofbvdd fsr g3 e1 fb_cs0 pb3 ? ? ? ofbvdd fsr g2 g3 i 2 c 0 i2c0_scl pb2 uart8_txd can0_tx ? i/o evdd ssr h12 g15 i2c0_sda pb1 uart8_rxd can0_rx ? i/o evdd ssr g12 g14 flexcan 1 can1_tx pb0 uart9_txd i2c1_scl ? i/o evdd ssr ? d14 can1_rx pc7 uart9_rxd i2c1_sda ? i/o evdd ssr ? d15 sdram controller sd_a14 ? ? ? ? o sdvdd st_dec ap ? p6 table 5. mcf5441 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pullup (u) 1 pulldown (d) direction 2 voltag e domain pad type 3 196 mapbga 4 256 mapbga mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice pin assignments and reset states freescale semiconductor 12 sd_a[13:0] ? ? ? ? o sdvdd st_dec ap p3, m1, m3, l2, l1, n4, m2, p2, l3, l4, n1, n2, k1, n3, a2, a1, a0 r4, r1, r3, n4, p3, t4, r2, t2, n3, p5, p4, n5, p2, t3 sd_ba[2:0] ? ? ? ? o sdvdd st_dec ap m6, l5, p4 p7, n6, r5 sd_cas ?? ?? o sdvdd st_dec ap l6 n8 sd_cke ? ? ? ? o sdvdd st_dec ap n6 r7 sd_clk ? ? ? ? o sdvdd st_ck p6 t5 sd_clk ?? ?? o sdvdd st_ck p7 t6 sd_cs ?? ?? o sdvdd st_dec ap m5 n7 sd_d[7:0] ? ? ? ? i/o sdvdd st_odt p11, m10, n10, m9, p10, m8, n8, m7 t12, r11, t11, r10, n9, t10, p9, r9 sd_dm ? ? ? ? o sdvdd st_odt p7 t7 sd_dqs ? ? ? ? i/o sdvdd st_dqs p8 t8 sd_dqs ?? ?? i/o sdvdd st_dqs p9 t9 sd_odt ? ? ? ? o sdvdd st_dec ap p5 p8 sd_ras ?? ?? o sdvdd st_dec ap m4 r6 sd_we ?? ?? o sdvdd st_dec ap n5 r8 sd_vref ? ? ? ? ? sdvdd st_vref n9 p10 sd_vtt ? ? ? ? ? sdvdd st_vtt l7 n10 external interrupts port irq7 pc6 ? ? ? i evdd ssr f12 f12 irq6 pc5 ? usb_clkin 12 ? i evdd ssr ? n1 irq4 pc4 dreq0 ?? ievddssr e11 f14 irq3 pc3 dspi0_pcs3 usbh_vbus_en ? ievddssr ? m1 irq2 pc2 dspi0_pcs2 usbh_vbus_oc ? 13 ievddssr ? m2 table 5. mcf5441 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pullup (u) 1 pulldown (d) direction 2 voltag e domain pad type 3 196 mapbga 4 256 mapbga pin assignments and reset states mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 13 irq1 pc1 ? ? ? ievddssr e13 f13 usb on-the-go usbo_dm ? ? ? ? i/o vdd_ usb0 ae b13 a14 usbo_dp ? ? ? ? i/o vdd_ usb0 ae a13 b14 usb host usbh_dm ? ? ? ? i/o vdd_ usbh ae ? a15 usbh_dp ? ? ? ? i/o vdd_ usbh ae ? b15 adc adc_in7/ dac1_out ? ? ? ? i vdda_ dac_ adc ae ? k3 adc_in[6:4] ? ? ? ? i vdda_ adc ae ? h2, j3, g4 adc_in3/ dac0_out ? ? ? ? i vdda_ dac_ adc ae ? k4 adc_in[2:0] ? ? ? ? i vdda_ adc ae ? j2, j1, h1 real time clock rtc_extal ? ? ? ? i 5 vstby ae b14 b16 rtc_xtal ? ? ? ? o vstby ae c14 c16 dspi/sbf 14 dspi0_pcs1/ sbf_cs pc0 ? ? ? i/o evdd msr k3 l1 dspi0_pcs0/ss pd7 i2c3_sda sdhc_dat3 ? i/o evdd msr j1 k2 dspi0_sck/ sbf_ck pd6 i2c3_scl sdhc_clk ? i/o evdd msr j3 l2 dspi0_sin/ sbf_di pd5 uart3_rxd sdhc_cmd u 15 i evdd msr k2 l3 dspi0_sout/ sbf_do pd4 uart3_txd sdhc_dat0 ? o evdd msr j2 k1 table 5. mcf5441 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pullup (u) 1 pulldown (d) direction 2 voltag e domain pad type 3 196 mapbga 4 256 mapbga mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice pin assignments and reset states freescale semiconductor 14 one wire ow_dat rgpio0/pd3 dack0 ? ? i/o evdd ssr m11 n11 dma timers t3in/pwm_exta3 rgpio1/p d2 t3out usbo_vbus_en/ ulpi_dir 16 ? ievddmsr g13 g13 t2in/pwm_exta2 rgpio2/pd1 t2out sdhc_dat2 ? i evdd msr j12 h14 t1in/pwm_exta1 rgpio3/pd0 t1out sdhc_dat1 ? ievddmsr h13 h13 t0in/pwm_exta0 rgpio4/ pe7 t0out usbo_vbus_oc/ ulpi_nxt 17 ? 18 i evdd msr j13 h15 uart 2 uart2_cts rgpio14/pe6 uart 6_txd ssi1_bclk ? ievddmsr ? m4 uart2_rts rgpio15/pe5 uart6_rxd ssi1_fs ? oevddmsr ? m3 uart2_rxd pe4 pwm_a3 ssi1_rxd ? ievddmsr ? p1 uart2_txd pe3 pwm_b3 ssi1_txd ? i/o 19 evdd msr ? n2 uart 1 uart1_cts rgpio7/pe2 uart5_txd dspi3_sck ? ievddmsr d11 c10 uart1_rts rgpio8/pe1 uart5_rxd dspi3_pcs0 ? oevddmsr c12 d10 uart1_rxd pe0 i2c5_sda dspi3_sin ? i evdd msr b10 c9 uart1_txd pf7 i2c5_scl dspi3_sout ? i/o 19 evdd msr c10 d9 uart 0 uart0_cts rgpio5/pf6 uart4_txd dspi2_sck ? ievddmsr e12 e13 uart0_rts rgpio6/pf5 uart4_rxd dspi2_pcs0 ? oevddmsr d12 b11 uart0_rxd pf4 i2c4_sda dspi2_sin ? ievddmsr c11 b10 uart0_txd pf3 i2c4_scl dspi2_sout ? i/o 19 evdd msr b11 d11 enhanced secure digital host controller sdhc_dat3 pf2 pwm_a1 dspi1_pcs0 ? i/o evdd msr ? b13 sdhc_dat2 pf1 pwm_b1 dspi1_pcs2 ? i/o evdd msr ? e14 sdhc_dat1 pf0 pwm_a2 dspi1_pcs1 ? i/o evdd msr ? d12 sdhc_dat0 pg7 pwm_b2 dspi1_sout ? i/o evdd msr ? b12 sdhc_cmd pg6 pwm_b0 dspi1_sin ? i/o evdd msr ? c11 sdhc_clk pg5 pwm_a0 dspi1_sck ? o evdd msr ? a10 table 5. mcf5441 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pullup (u) 1 pulldown (d) direction 2 voltag e domain pad type 3 196 mapbga 4 256 mapbga pin assignments and reset states mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 15 smart card interface 0 sim0_data rgpio13/pg4 pwm_fault2 sdhc_dat7 ? i/o evdd msr ? e12 sim0_ven rgpio12/pg3 pwm_fault0 ? ? o evdd msr ? d13 sim0_rst rgpio11/pg2 p wm_force sdhc_dat6 ? o evdd msr ? c15 sim0_pd rgpio10/pg1 pwm_sync sdhc_dat5 ? i evdd msr ? c14 sim0_clk rgpio9/pg0 pwm_fault1 sdhc_dat4 ? o evdd msr ? a11 synchronous serial interface 0 ssi0_rxd ph7 i2c2_sda sim1_ven ? i evdd msr b12 c12 ssi0_txd ph6 i2c2_scl sim1_data ? o evdd msr a11 c13 ssi0_fs ph5 uart7_txd sim1_rst ? i/o evdd msr c13 e15 ssi0_mclk ph4 ssi_clkin sim1_clk ? o evdd msr a12 a12 ssi0_bclk ph3 uart7_rxd sim1_pd ? i/o evdd msr d13 a13 ethernet subsystem mii0_mdc pi1 rmii0_mdc 20 ??o evdd fsr n14 p16 mii0_mdio pi0 rmii0_mdio 20 ??i/o evdd fsr m14 n16 mii0_rxdv pj7 rmii0_crs_dv 20 ??i evdd fsr m13 p14 mii0_rxd[1:0] pj[6:5] rmii0_rxd[1:0] 20 ??i evdd fsr p13, n13 r15, t15 mii0_rxer pj4 rmii0_rxer 20 ??i evdd fsr m12 n14 mii0_txd[1:0] pj[3:2] rmii0_txd[1:0] 20 ??o evdd fsr p12, n12 r13, p13 mii0_txen pj1 rmii0_txen 20 ?d 21 o evdd fsr n11 p12 mii0_col pj0 rmii1_mdc ulpi_stp ? i evdd fsr ? r12 mii0_txer pk7 rmii1_mdio ulpi_data4 ? o evdd fsr ? r14 mii0_crs pk6 rmii1_crs_dv ulpi_data5 ? i evdd fsr ? p11 mii0_rxd[3:2] pk[5:4] rmii1_r xd[1:0] ulpi_data[1:0] ? i evdd fsr ? p15, n13 mii0_rxclk pk3 rmii1_rxer ulpi_data6 ? i evdd fsr ? m14 mii0_txd[3:2] pk[2:1] rmii1_t xd[1:0] ulpi_data[3:2] ? o evdd fsr ? t13, n12 mii0_txclk pk0 rmii1_txen ulpi_data7 d 21 i evdd fsr ? t14 bdm/jtag allpst 22 ph2 ? ? ? oevdd fsr k12 ? ddata[3:2] ph[1:0] ? ? ? o evdd fsr ? l15, m13 ddata[1:0] pi[7:6] ? ? ? o evdd fsr ? m15, l14 table 5. mcf5441 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pullup (u) 1 pulldown (d) direction 2 voltag e domain pad type 3 196 mapbga 4 256 mapbga mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice pin assignments and reset states freescale semiconductor 16 pst[3:0] pi[5:2] ? ? ? o evdd fsr ? j13, j16, j15, j14 jtag_en ? ? ? d i evdd msr l9 n15 pstclk ? tclk 23 ?? ievddfsr l14 m16 dsi ? tdi 23 ?u ievddmsr l11 l13 dso ? tdo 23 ?? o evdd msr l12 k14 bkpt ?tms 23 ?u ievddmsr k13 k16 dsclk ? trst 23 ?u i evdd msr l10 k13 test (this signal must be grounded) test ? ? ? d ievddssr l8 r16 power supplies ivdd ? ? ? ? ? ? ? d9, d10, e9, e10, f9, f10, g10 e9?e11, f9?f11 evdd ? ? ? ? ? ? ? f4?f7, g6, g7, h6, h7, j5, j6 h8, j7?j10, k6?k11, l6 fb_vdd ? ? ? ? ? ? ? d5?d7, e4?e7 e5?e7, f5, f6, g5 sd_vdd ? ? ? ? ? ? ? j8?j10, k7?k10 m7?m12 vdd_osc_a_pll ? ? ? ? ? ? vddint f13 f15 vss_osc_a_pll ? ? ? ? ? ? vddint f14 f16 vdd_usbo ? ? ? ? ? ? vdde f11 g12 vdd_usbh ? ? ? ? ? ? vdde ? h12 vdda_adc ? ? ? ??? ? ? h4 vssa_adc ? ? ? ??? vssint ? h5 table 5. mcf5441 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pullup (u) 1 pulldown (d) direction 2 voltag e domain pad type 3 196 mapbga 4 256 mapbga pin assignments and reset states mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 17 vdda_dac_adc ? ? ? ?? ? vddint ? j4 vssa_dac_adc ? ? ? ?? ? vssint ? j5 vstby 24 ?? ???? vddint e14 e16 vss ? ? ? ? ? ? ? a1, a14, d8, d14, e8, f8, g4, g8, g9, g11, h4, h8?11, j4, j7, j11, j14, k4?k6, k11, p1, p14 a1, a16, d16, e8, f7, f8, g6?g11, h6, h7, h9?h11, j6, j11, j12, k12, l4, l7?l12, m5, m6, t1, t16 1 all pins available with gpio contain a configurable pull-up/d own. this column indicates the pull devices that are enabled automatically at reset. pull-ups are generally only enable d on pins with their primary function, except as noted. 2 refers to pin?s primary function. 3 for details on the available slew rates of the various pad types see section ?output pad loading and slew rate? of the mcf5441x data sheet or section ?slew rate control registers (srcr_x)? in chapter ?pin-multiplexing and control? of the mcf5441x reference manual. 4 this is tentative information ? as of september 21 , 2010 the 196 mapbga ball map has not yet been finalized. 5 enabled as input only in oscillator bypass mode (internal crystal oscillator is disabled). 6 these pins are time-division multiplexed between the flexbus and nfc. an arbitration mechanism determines which module drives these pins at any point in time. 7 an internal pulldown circuit is enab led during system reset for fb_ad[10]. 8 an internal pullup circuit is enabl ed when the system is in reset state. 9 configurable pull that is enabled and pulled up after reset. 10 when configured for fb_a1, this pin is time-division multip lexed between the flexbus and nfc. an arbitration mechanism determines which module drives the pin at any point in ti me. when not configured as fb_a1, nfc_ale cannot be used. 11 when configured for fb_a0, this pin is time-division multip lexed between the flexbus and nfc. an arbitration mechanism determines which module drives the pin at any point in time . when not configured as fb_a0, nfc_cle cannot be used. 12 since usb_clkin is a clock signal, it must be dedicated to the usb system. do not implement this pin as dual-use. 13 when alternate 2 is selected, then internal pullup/pulldown control will come from the misccr[3] register of cim. 14 when booting from serial boot flash, the sbf function is enabled automatically. after the sbf function completes its reset sequ ence, the signals are returned to gpio functionality. 15 automatic pull-up when sbf controls the pin during reset only. configurable pull when uart, dspi, or sdhc control the pin. 16 if ulpi is enabled, ulpi_dir is available as the alternate 2 function. if ulpi is disabled, usbo_vbus_en is available. 17 if ulpi is enabled, ulpi_nxt is available as the alternat e 2 function. if ulpi is disabl ed, usbo_vbus_oc is available. 18 when alternate 2 is selected, then internal pullup/pulldown control will come from the misccr[2] register of cim. 19 uart x _txd pad can act as rxd(input) pad when uart one wire mode is enabled. 20 these rmii functions are selected by the mode chosen by the mac-net, not by the pin-multiplexing and control (gpio) module. 21 configurable pull that is enabled and pulled down after reset. table 5. mcf5441 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pullup (u) 1 pulldown (d) direction 2 voltag e domain pad type 3 196 mapbga 4 256 mapbga mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice pin assignments and reset states freescale semiconductor 18 3.2 pinout?196 mapbga the tentative pinout for the mcf54 410 package is below. the signal assignments have not been finalized. 22 the allpst signal is available only on the 196 mapbga packa ge and allows limited debug trace functionality compared to the 256 mapbga package. 23 if jtag_en is asserted, these pins default to alternate 1 (jta g) functionality. the gpio module is not responsible for assignin g these pins. 24 vstby is for optional standby lithium battery. if not used, connect to evdd. 1234567891011121314 a vss fb_ ad10 fb_ ad14 fb_ ad16 fb_ ad18 fb_ ad19 fb_ ad24 fb_ ad27 fb_ ad30 fb_ ad31 ssi0_ txd ssi0_ mclk usbo_ dp vss a b fb_ ad6 fb_ ad9 fb_ ad11 fb_ ad13 fb_ ad17 fb_ ad20 fb_ ad23 fb_ ad26 fb_ ad29 uart1_ rxd uart0_ txd ssi0_ rxd usbo_ dm rtc_ extal b c fb_ ad3 fb_ ad5 fb_ ad8 fb_ ad12 fb_ ad15 fb_ ad21 fb_ ad22 fb_ ad25 fb_ ad28 uart1_ txd uart0_ rxd uart0_ rts ssi0_ fs rtc_ xtal c d fb_ ad0 fb_ ad2 fb_ ad4 fb_ ad7 fb_ vdd fb_ vdd fb_ vdd vss ivdd ivdd uart1_ rts uart1_ cts ssi0_ bclk vss d e fb_be/ bwe2 fb_ale fb_ ad1 fb_ vdd fb_ vdd fb_ vdd fb_ vdd vss ivdd ivdd irq4 uart0_ cts irq1 vstby_ rtc e f fb_be/ bwe0 fb_be/ bwe1 fb_be/ bwe3 evdd evdd evdd evdd vss ivdd ivdd vdd_ usbo irq7 vdd_ osc_a _pll vss_ osc_a _pll f g fb_clk fb_cs0 fb_cs1 vss boot mod1 evdd evdd vss vss ivdd vss i2c0_ sda t3in extal g h fb_oe fb_r/w fb_ta vss boot mod0 evdd evdd vss vss vss vss i2c0_ scl t1in xtal h j dspi0_ pcs0 dspi0_ sout dspi0_ sck vss evdd evdd vss sd_ vdd sd_ vdd sd_ vdd vss t2in t0in vss j k sd_a1 dspi0_ sin dspi0_ pcs1 vss vss vss sd_ vdd sd_ vdd sd_ vdd sd_ vdd vss allpst tms reset k l sd_a9 sd_a10 sd_a5 sd_a4 sd_ba1 sd_cas sd_vtt test jtag_ en trst tdi tdo rstout tclk l m sd_a12 sd_a7 sd_a11 sd_ras sd_cs sd_ba2 sd_d0 sd_d2 sd_d4 sd_d6 ow_ dat rmii0_ rxer rmii0_ crs_dv rmii0_ mdio m n sd_a3 sd_a2 sd_a0 sd_a8 sd_we sd_cke sd_dqm sd_d1 sd_vre f sd_d5 rmii0_ txd0 rmii0_ txen rmii0_ rxd0 rmii0_ mdc n p vss sd_a6 sd_a13 sd_ba0 sd_odt sd_clk sd_clk sd_dqs sd_dqs sd_d3 sd_d7 rmii0_ txd1 rmii0_ rxd1 vss p 1234567891011121314 figure 7. mcf54410 pinout (196 mapbga) pin assignments and reset states mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 19 3.3 pinout?256 mapbga the pinout for the mcf54415, mcf54416, mcf54417, and mcf54418 packages are shown below. 12345678910111213141516 a vss fb_ ad3 fb_ ad13 fb_ ad14 fb_ ad16 fb_ ad20 fb_ ad22 fb_ ad26 fb_ ad29 sdhc_ clk sim0_ clk ssi0_ mclk ssi0_ bclk usbo_ dm usbh_ dm vss a b fb_ cs4 fb_ ad2 fb_ ad8 fb_ ad11 fb_ ad15 fb_ ad19 fb_ ad24 fb_ ad28 fb_ ad31 uart0_ rxd uart0_ rts sdhc_ dat0 sdhc_ dat3 usbo_ dp usbh_ dp rtc_ extal b c fb_be/ bwe3 fb_ ad1 fb_ ad7 fb_ ad9 fb_ ad10 fb_ ad17 fb_ ad23 fb_ ad30 uart1_ rxd uart1_ cts sdhc_ cmd ssi0_ rxd ssi0_ txd sim0_ pd sim0_ rst rtc_ xtal c d fb_be/ bwe1 fb_ ale fb_ ad5 fb_ ad12 fb_ ad18 fb_ ad21 fb_ ad25 fb_ ad27 uart1_ txd uart1_ rts uart0_ txd sdhc_ dat1 sim0_ ven can1_ tx can1_ rx vss d e fb_ cs1 fb_ be/bw e2 fb_ ad4 fb_ ad6 fb_ vdd fb_ vdd fb_ vdd vss ivdd ivdd ivdd sim0_ xmt uart0 _cts sdhc_ dat2 ssi0_ fs vstby_ rtc e f fb_ oe fb_ cs5 fb_ ad0 fb_be/ bwe0 fb_ vdd fb_ vdd vss vss ivdd ivdd ivdd irq7 irq1 irq4 vdd_ osc_a _pll vss_ osc_a _pll f g fb_ clk fb_ r/w fb_ cs0 adc_ in4 fb_ vdd vss vss vss vss vss vss vdd_ usbo t3in i2c0_ sda i2c0_ scl extal g h adc_ in0 adc_ in6 fb_ ta avdd_ adc avss_ adc vss vss evdd vss vss vss vdd_ usbh t1in t2in t0in xtal h j adc_ in1 adc_ in2 adc_ in5 vdda_ dac_ adc vssa_ dac_ adc vss evdd evdd evdd evdd vss vss pst3 pst0 pst1 pst2 j k dspi0_ sout dspi0_ pcs0 adc_ in7 adc_ in3 boot mod1 evdd evdd evdd evdd evdd evdd vss trst tdo reset tms k l dspi0_ pcs1 dspi0_ sck dspi0_ sin vss boot mod0 evdd vss vss vss vss vss vss tdi ddata0 ddata3 rst out l m irq3 irq2 uart2_ rts uart2_ cts vss vss sd_ vdd sd_ vdd sd_ vdd sd_ vdd sd_ vdd sd_ vdd ddata2 mii0_ rxclk ddata1 tclk m n irq6 uart2_ txd sd_a5 sd_a10 sd_a2 sd_ba1 sd_cs sd_ cas sd_d3 sd_vtt ow_ io mii0_ txd2 mii0_ rxd2 mii0_ rxer jtag_ en mii0_ mdio n p uart2_ rxd sd_a1 sd_a9 sd_a3 sd_a4 sd_a14 sd_ba2 sd_ odt sd_d1 sd_ vref mii0_ crs mii0_ txen mii0_ txd0 mii0_ rxdv mii0_ rxd3 mii0_ mdc p r sd_a12 sd_a7 sd_a11 sd_a13 sd_ba0 sd_ ras sd_ cke sd_we sd_d0 sd_d4 sd_d6 mii0_ col mii0_ txd1 mii0_ txer mii0_ rxd1 test r t vss sd_a6 sd_a0 sd_a8 sd_ clk sd_ clk sd_ dm sd_ dqs sd_ dqs sd_d2 sd_d5 sd_d7 mii0_ txd3 mii0_ txclk mii0_ rxd0 vss t 12345678910111213141516 figure 8. mcf54415, mcf54416, mcf54417, and mcf54418 pinout (256 mapbga) mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 20 4 electrical characteristics this document contains electrical specification tables and reference timing diagrams for the mcf5441 x microprocessor. this section contains detailed informa tion on ac/dc electrical characteristics and ac timing specifications. note the specifications for this device in an y other document are superseded by the specifications in this document. 4.1 absolute maximum ratings table 6. absolute maximum ratings 1, 2 1 functional operating conditions are given in ta b l e 1 1 . absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. continued operation at these levels may affect device reliability or cause permanent damage to the device. 2 this device contains circuitry protecting against damage due to high static volt age or electrical fields. however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. immunity to static and electrical fields is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., v ss or ev dd ). rating symbol pin name value units external i/o pad supply voltage ev dd evdd ?0.3 to +4.0 v internal logic supply voltage iv dd ivdd ?0.5 to +2.0 v flexbus i/o pad supply voltage fbv dd fb_vdd ?0.3 to +4.0 v sdram i/o pad supply voltage sdv dd sd_vdd ?0.3 to +4.0 v pll supply voltage pv dd vdd_osc_a_pll ?0.3 to +4.0 v usb otg supply voltage usbv dd vdd_usbo ?0.3 to +4.0 v usb host supply voltage usbv dd vdd_usbh ?0.3 to +4.0 v adc supply voltage av dd vdda_adc ?0.3 to +4.0 v dac and adc supply voltage ? vdda_dac_adc ?0.3 to +4.0 v rtc standby supply voltage rtcv stby vstby_rtc ?0.3 to +4.0 v digital input voltage 3 3 input must be current limited to the va lue specified. to determine the value of the required current -limiting resistor, calculate resistance values for positive and negative clam p voltages, and then use the larger of the two values. v in ? ?0.3 to +3.6 v instantaneous maximum current single pin limit (applies to all pins) 3, 4, 5 4 all functional non-supply pins are internally clamped to v ss and ev dd . 5 power supply must maintain regulation within operating ev dd , fbv dd , and sdv dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > ev dd , fbv dd , or sdv dd ) is greater than i dd , the injection current may flow out of ev dd , fbv dd , or sdv dd and could result in external power supply going out of regulation. ensure the external ev dd , fbv dd , or sdv dd load shunts current greater than maximum injection current. this is the greatest risk when the mpu is not consuming power (for example, no clock). i dd ?25ma operating temperature range (packaged) t a (t l ? t h ) ? ?40 to +85 ? c storage temperature range t stg ? ?55 to +150 ? c electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 21 4.2 thermal characteristics the average chip-junction temperature (t j ) in ? c can be obtained from: eqn. 1 where: t a = ambient temperature, ? c q jma = package thermal resistance, junction-to-ambient, ? c/w p d =p int + p i/o p int =i dd ? iv dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be ignored. an approx imate relationship between p d and t j (if p i/o is neglected) is: eqn. 2 solving equations 1 and 2 for k gives: eqn. 3 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . table 7. thermal characteristics characteristic symbol 196 mapbga 256 mapbga unit junction to ambient, natural convection 1,2 1 ? ja and ? jt parameters are simulated in conformance with eia/jesd standard 51-2 for natural convection. junction temperature is a function of die size, on-chi p power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air fl ow, power dissipation of other components on the board, and board thermal resistance. 2 per jedec jesd51-6 with the board horizontal. four layer board (2s2p) ? ja tbd 32 ? c / w junction to ambient (@200 ft/min) 1,2 four layer board (2s2p) ? jma tbd 29 ? c / w junction to board 3 3 thermal resistance between the die and the printed circ uit board in conformance with jedec jesd51-8. board temperature is measured on the top su rface of the board near the package. ? jb tbd 22 ? c / w junction to case 4 4 thermal resistance between the die and the case top su rface as measured by the cold plate method (mil spec-883 met hod 1012.1). ? jc tbd 12 ? c / w junction to top of package 1,5 5 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51 -2. when greek letters are not avai lable, the thermal characterization parameter is written in conformance with psi-jt. ? jt tbd 2 ? c / w maximum operating junction temperature t j 105 105 o c t j t a p d ? jma ? ?? + = p d k t j 273 ? c + ?? -------------------------------- - = kp d t a 273 ? c ? ?? q jma p d 2 ? + ? = mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 22 4.3 esd protection 4.4 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply over voltage is applied to each power supply pin. ? a current injection is applied to each input, output, and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 4.5 dc electrical specifications table 8. esd protection characteristics 1, 2 1 all esd testing is in conformity with jesd22 stress test qualification. 2 a device is defined as a failure if after ex posure to esd pulses the device no longer meets the device specification requirements. comp lete dc parametric and functional testing is performed per applicable specification at room temperature followed by hot temperature, unless specified otherwise in the device sp ecifications provided in this document. characteristics symbol value units esd target for human body model hbm 2000 v table 9. latch-up results no. symbol parameter conditions class 1 lu cc static latch-up class t a = 125 c conforming to jesd 78 ii level a 2 adc_in7/ dac1_out cc static latch-up class t a = 125 c conforming to jesd 78 up to 40 ma ii level a table 10. power supply specifications characteristic symbol pin name min max units internal logic supply voltage, nominal 1.2 v iv dd ivdd 1.14 1.32 v flexbus supply voltage nominal 1.8?3.3 v fbv dd fb_vdd 1.71 3.63 v sdram supply voltage ddr2 @ 1.8 v sdv dd sd_vdd 1.71 1.98 v sdram input reference voltage sdv ref sd_vref 0.49 x sdv dd 0.51 x sdv dd v sdram termination supply voltage sdv tt sd_vtt sdv ref ?0.04 sdv ref +0.04 v pll analog operation voltage range, nominal 3.3 v pv dd vdd_osc_ a_pll 3.135 3.63 v external i/o pad supply voltage, nominal 3.3 v ev dd evdd 3.135 3.63 v electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 23 usb supply voltage, nominal 3.3 v usbv dd vdd_usbo vdd_usbh 3.135 3.63 v adc supply voltage av dd vdda_adc 3.135 3.63 v dac supply voltage ? vdda_dac_ adc 3.135 3.63 v rtc standby supply voltage rtcv stby vstby_rtc 1.6 ev dd ?0.2v v table 11. i/o electrical specifications characteristic symbol min max units cmos input high voltage ev ih 0.51 ? ev dd ev dd +0.3 v cmos input low voltage ev il v ss ? 0.3 0.42 ? ev dd v cmos output high voltage i oh = ?2.0 ma ev oh 0.8 ? ev dd ?v cmos output low voltage i ol = 2.0 ma ev ol ?0.2 ? ev dd v sdram input high voltage ddr2 @ 1.8v sdv ih sdv dd ? 0.7 sdv dd +0.3 v sdram input low voltage ddr2 @ 1.8v sdv il ? 0.3 sdv dd ? 0.3 v sdram output high voltage ddr2@ 1.8v i oh = ?13.4 ma sdv oh sdv dd ? 0.9 ? v sdram output low voltage ddr2@ 1.8v i oh = 13.4 ma sdv ol ?sdv dd ? 0.1 v flexbus input high voltage @ 1.8v?3.3v fbv ih 0.51 ? fbv dd fbv dd +0.3 v flexbus input low voltage @ 1.8v?3.3v fbv il v ss ? 0.3 0.42 ? fbv dd v flexbus output high voltage @ 1.8v?3.3v i oh = ?5.0 ma for all modes fbv oh 0.8 ? fbv dd ?v flexbus output low voltage @ 1.8v?3.3v i ol = 5.0 ma for all modes fbv ol ?0.2 ? fbv dd v input leakage current v in = v dd or v ss , input-only pins i in ?2.5 2.5 ? a weak internal pull-up/pull-down device current 1 i apu 10 315 ? a table 10. power supply specifications (continued) characteristic symbol pin name min max units mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 24 4.6 output pad loading and slew rate the output pins on the mcf5441x devices have programmable slew rates. table 12 lists the rise/fall time for pins based on the type of pad used for the signal, the value programmed into the ap propriate field of the slew rate control registers, and capaci tive loading. refer to table 5 for a list of the external signals to pad connections. note to allow the i/o interfaces to run at their maxi mum frequency, set their respective slew rate select values to 11. selectable weak internal pull-up/pull-down device current 1 i apu 25 150 ? a input capacitance 2 all input-only pins all input/output (three-state) pins c in ? ? 7 7 pf output loading for cmos pads (ev dd and fbv dd domains) low drive high drive c l 50 200 pf output loading for sdramc pads (sdv dd domain) low drive high drive c l 5 50 pf 1 refer to the signals section for pins having weak internal pull-up devices. 2 this parameter is characterized before qualification rather than 100% tested. table 12. output pad slew rates pad type 1 slew rate select field value drive load (pf) rise/fall time (ns) ssr 11 50 2.2 200 6 10 50 22 200 28 01 50 42 200 50 00 50 210 200 220 table 11. i/o electrical specifications (continued) characteristic symbol min max units electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 25 4.7 ddr pad drive strengths the ddr pins on the mcf5441x devices have programmable drive strengths. table 13 lists the drive strengths for pins based on the value programmed into the appropriate field of the drive strength control register. refer to table 5 for a list of the external signals to pad connections. note for a single device drive, this setting should be 10 to enable full strength mode. high strength is intended for multiple device drives (dimm). msr 11 50 1.2 200 6 10 50 9 200 14 01 50 17 200 23 00 50 110 200 120 fsr 11 50 1.1 200 2.6 10 50 2.4 200 5 01 50 5 200 8 00 50 16 200 21 1 the ae pads are used for usb communication and are governed by usb.org specifications. they are not included in this table. table 13. ddr pad drive strengths pad type drive strength select field value drive strength st 11 ddr2 high strength 10 ddr2 full strength 01 not supported 00 not supported table 12. output pad slew rates (continued) pad type 1 slew rate select field value drive load (pf) rise/fall time (ns) mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 26 4.8 oscillator and pll electrical characteristics reference figure 9 for crystal circuits. table 14. pll electrical characteristics num characteristic symbol min max unit 1 pll reference frequency range 1 crystal reference external reference f ref_crystal f ref_ext 14 1 14 1 50 1 50 1 1 these reference value ranges are for after a pll predivider (p rediv), which can be programmed to 1, 2, 4, 8, or 16. the prediv value can be set while booting from serial flash. in parallel reset configuration, the prediv value is set to one. in this mode, if the input frequency results in an ou t of range reference frequency, boot the processor in limp mode, set the proper prediv and multipli er settings, and switch to pll mode. mhz mhz 2 core frequency fb_clk frequency 2 (misccr2[fbhalf] = 0) 2 all internal registers retain data at 0 hz. f sys f sys/2 120 60 250 100 mhz mhz 3 vco frequency f vco 240 500 mhz 4 dcc frequency 3 3 required only for ddr2 memory. f dcc 300 500 mhz 5 crystal start-up time 4, 5 4 this parameter is guaranteed by characterization before qualification rat her than 100% tested. 5 proper pc board layout procedures must be followed to achieve specifications. t cst ?10ms 6 extal input high voltage external and limp modes v ihext ev ih evdd v 7 extal input low voltage external and limp modes v ilext 0ev il v 8pll lock time 4, 6 6 this specification is the pll lock time only and does not include oscillator start-up time. t lpll ?50ms 9 duty cycle of reference 4 t dc ?45% +45% % 10 crystal capacitive load c l ? from crystal spec pf 11 feedback resistor r f 10 ? m ? 12 series resistor r s 0 200 ? 13 discrete load capacitance for xtal c l_xtal ?2 ? c l ? c s_xtal ? c pcb_xtal 7 7 c pcb_extal and c pcb_xtal are the measured pcb stray capacitances on extal and xtal, respectively. pf 14 discrete load capacitance for extal c l_extal ?2 ? c l ? c s_extal ? c pcb_extal 7 pf 15 fb_clk period jitter, 4, 5, 7, 8, measured at f sys max peak-to-peak jitter (clock edge to clock edge) long term jitter 8 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device po wered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via pll v dd , ev dd , and v ss and variation in crystal oscillator frequency increase the cjitter percentage for a given interval. c jitter ? ? 10 0.1 % f sys/3 % f sys/3 electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 27 figure 9. typical crystal circuit 4.9 reset timing specifications table 15 lists specifications for the reset timing parameters shown in figure 10 . table 15. reset and configuration override timing num characteristic min max unit r1 1 1 reset and configuration override data lines are synchronized internally. setup and hold times must be met only if recognition on a particular clock is required. reset valid to fb_clk (setup) 9 ? ns r2 fb_clk to reset invalid (hold) 1.5 ? ns r3 reset valid time 2 2 during low power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. 5 ? fb_clk cycles r4 fb_clk to rstout valid ? 10 ns r5 rstout valid to configuration override inputs valid 0 ? ns r6 configuration override inputs valid to rstout invalid (setup) 20 ? fb_clk cycles r7 configuration override inputs invalid after rstout invalid (hold) 0 ? ns r8 rstout invalid to configuration override inputs high impedance ? 1 fb_clk cycles r9 minimum rstout pulse width 512 ? fb_clk cycles xosc extal xtal crystal or resonator r s c 2 r f c 1 c l c l mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 28 figure 10. reset and configuration override timing 4.10 flexbus timing specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output cloc k (fb_clk). all other timing relationships can be derived from these values. all flexbus signals use pad type pad_fsr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. 1 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. table 16. flexbus timing specifications num characteristic min max unit notes frequency of operation ? 62.5 mhz fb1 clock period 16 ? ns fb2 output valid ? 6.0 ns 1 1 specification is valid fo r all fb_ad[31:0], fb_r/w , fb_ale, fb_ts , fb_cs n , fb_oe , fb_be/bwe n , and fb_tsiz[1:0]. fb3 output hold 0.5 ? ns 1 fb4 input setup 5.5 ? ns 2 2 specification is valid for all fb_ad[31:0] and fb_ta . fb5 input hold 0 ? ns 2 r1 r2 fb_clk reset rstout r3 r4 r8 r7 r6 r5 r4 bootmod[1:0] r9 electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 29 figure 11. flexbus read timing fb_clk fb_r/w s0 s1 s2 s3 fb_ale fb_tsiz[1:0] tsiz[1:0] fb_ad[ y :0] fb_ad[31: x ] fb_cs n , fb_oe , fb_be/bwe n fb_ta data addr[31: x ] addr[ y :0] fb3 fb1 fb2 fb5 fb4 fb5 fb4 fb_ts note: 1 fb2 and fb3 output specifications are valid for all fb_ad[31:0], fb_r/w , fb_ale, fb_ts , fb_cs n , fb_oe , fb_be/bwe n , and fb_tsiz[1:0]. 2 fb4 and fb5 input specifications ar e valid for all fb_ad[31:0] and fb_ta . mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 30 figure 12. flexbus write timing 4.11 nand flash controller (nfc) timing specifications the nand flash controller (nfc) implemen ts the interface to standard nand flash memory devices. this section describes the timing parameters of the nfc. all nfc signals use pad type pad_fsr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. 1 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. table 17. nfc timing specifications num characteristic symbol min max unit frequency of operation ? 40 1 mhz nf1 clock period t nfc 25 ? ns nf2 nfc_cle setup time t cls 1.5 ? t nfc ?ns nf3 nfc_cle hold time t clh t nfc ?ns nf4 nfc_ce setup time t cs 1.5 ? t nfc ?ns nf5 nfc_ce hold time t ch t nfc ?ns nf6 nfc_we pulse width t wp 0.5 ? t nfc ? 0.5 ? ns fb_clk fb_r/w fb_ale fb_oe s0 s2 s3 data fb_tsiz[1:0] tsiz[1:0] s1 addr[31: x ] fb_ad[ y :0] fb_ad[31: x ] addr[ y :0] fb_cs n , fb_be/bwe n fb_ta fb3 fb1 fb2 fb5 fb4 fb_ts note: 1 fb2 and fb3 output specifications are valid for all fb_ad[31:0], fb_r/w , fb_ale, fb_ts , fb_cs n , fb_oe , fb_be/bwe n , and fb_tsiz[1:0]. 2 fb4 and fb5 input specifications are valid for all fb_ad[31:0] and fb_ta . electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 31 figure 13. command latch cycle timing nf7 nfc_ale setup time t als 1.5 ? t nfc ?ns nf8 nfc_ale hold time t alh t nfc ?ns nf9 data setup time t ds 0.5 ? t nfc ? 4 ? ns nf10 data hold time t dh 0.5 ? t nfc ?10 ? ns nf11 write cycle time t wc t nfc ?ns nf12 nfc_we high hold time t wh 0.5 ? t nfc ?1 ? ns nf13 ready to nfc_re low t rr 4.5 ? t nfc ?ns nf14 nfc_re pulse width t rp 0.5 ? t nfc ? 0.5 ? ns nf15 read cycle time t rc t nfc ?ns nf16 nfc_re high hold time t reh 0.5 ? t nfc ?1 ? ns nf17 data in setup time t dsu 6?ns 1 50 mhz maximum frequency can only be used if the part is in edo (enhanced data out) mode. table 17. nfc timing specifications (continued) num characteristic symbol min max unit nfc_cle nfc_ce nfc_we nfc_ale nfc_io[7:0] command nf2 nf3 nf4 nf6 nf5 nf9 nf8 nf7 nf10 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 32 figure 14. address latch cycle timing figure 15. write data latch timing nfc_cle nfc_ce nfc_we nfc_ale nfc_io[7:0] address nf2 nf4 nf5 nf6 nf7 nf8 nf9 nf10 nf11 nf12 nfc_cle nfc_ce nfc_we nfc_ale nfc_io[15:0] data to nf nf3 nf5 nf6 nf9 nf10 nf11 nf12 nf7 electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 33 figure 16. read data latch timing 4.12 ddr sdram controller timing specifications the following timing numbers must be followed to properly latch or drive data onto the sdram memory bus. all timing numbers are relative to the dqs byte lanes. table 18. sdram timing specifications num characteristic symbol min max unit notes frequency of operation 100 250 mhz 1 1 the sdram interface operates at the sa me frequency as the internal system bus. dd1 clock period t sdck 4.0 10.0 ns dd2 pulse width high t sdckh 0.45 0.55 t sdck 2 2 pulse width high plus pulse width low cannot exceed min and max clock period. dd3 pulse width low t sdckl 0.45 0.55 t sdck 3 dd4 address, sd_cke, sd_cas , sd_ras , sd_we , sd_cs [1:0] ? output valid t cmv ?0.5 ? t sdck + 1 ns 3 3 command output valid should be 1/2 the memory bus clock (t sdck ) plus some minor adjustments for process, temperature, and voltage variations. dd5 address, sd_cke, sd_cas , sd_ras , sd_we , sd_cs [1:0] ? output hold t cmh 0.5 ? t sdck ? 1 ? ns dd6 write command to first dqs latching transition t dqss ?wl+0.2 ? t sdck ns dd7 data and data mask output setup (dq ? dqs) relative to dqs (ddr write mode) t qs 0.4 ? ns 4 5 dd8 data and data mask output hold (dqs ? dq) relative to dqs (ddr write mode) t qh 0.4 ? ns 6 dd9 input data skew relative to dqs (input setup) t is ?0.5ns 7 dd10 input data hold relative to dqs. t ih 0.375 ? t sdck ?ns 8 nfc_r/b nf13 nfc_ce nfc_re nfc_io[15:0] data from nf nf5 nf15 nf16 nf10 nf14 nf17 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 34 figure 17. ddr write timing 4 this specification relates to the requir ed input setup time of ddr memories. the microprocessor?s output setup should be larger than the input setup of the ddr memories. if it is not larger, then the input setup on the memory is in violation. sd_d[31:24] is relative to sd_dqs[3]; sd_d[23:16] is relative to sd_dqs[2] 5 the first data beat is valid before the first rising edge of dq s and after the dqs write preamble. the remaining data beats are valid for each subsequent dqs edge. 6 this specification relates to the required hold time of ddr memories. sd_d[31:24] is relative to sd_dqs[3]; sd_d[23:16] is relative to sd_dqs[2] 7 data input skew is derived from each dqs clock edge. it begi ns with a dqs transition and ends when the last data line becomes valid. this input skew must incl ude ddr memory output skew and system leve l board skew (due to routing or other factors). 8 data input hold is derived from each dqs clock edge. it begins with a dqs transition and ends when the first data line becomes invalid. sd_clk sd_cs n ,sd_we , sd_dm sd_d[7:0] sd_a[13:0] sd_ras , sd_cas cmd row dd1 dd5 dd4 col wd1 wd2 wd3 wd4 dd7 sd_dqs dd8 dd8 dd7 sd_clk dd3 dd2 dd6 electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 35 figure 18. ddr read timing 4.13 usb transceiver timing specifications the mcf5441 x device is compliant with industr y standard usb 2.0 specification. 4.14 ulpi timing specifications the ulpi interface is fully compliant wi th the industry standard utmi+ low pin interface. contro l and data timing requirements for the ul pi pins are given in table 19 . these timings apply to synchronous mode only. all timings are measured with respect to the clock as seen at the usb_clkin pin on the mcf5441 x . the ulpi phy is the source of the 60mhz clock. note the usb controller requires a 60-mhz clock, even if using the on-chip fs/ls transceiver instead of the ulpi interface. in this case, the 60-mhz clock can be generated by the pll or input on the usb_clkin pin. sd_clk sd_cs n ,sd_we , sd_dqs sd_d[7:0] sd_a[13:0] sd_ras , sd_cas cmd row dd1 dd5 dd4 rd1 rd2 rd3 rd4 sd_dqs dd9 sd_clk dd3 dd2 sd_d[7:0] rd1 rd2 rd3 rd4 dd10 cl=2 cl=2.5 col dqs read preamble dqs read postamble dqs read preamble dqs read postamble cl = 2.5 cl = 2 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 36 all ulpi signals use pad type pad_fsr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. 1 figure 19. ulpi timing diagram 4.15 esdhc timing specifications this section describes the elect rical information of the esdhc. all esdhc signals use pad type pad_msr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. 2 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. table 19. ulpi interface timing num characteristic min nominal max units usb_clkin operating frequency ? 60 ? mhz usb_clkin duty cycle ? 50 ? % u1 usb_clkin clock period ? 16.67 ? ns u2 input setup (control and data) 5.0 ? ? ns u3 input hold (control and data) 1.0 ? ? ns u4 output valid (control and data) ? ? 9.5 ns u5 output hold (control and data) 1.0 ? ? ns 2.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. ulpi_data[7:0] (data output) ulpi_data[7:0] (data input) ulpi_dir / ulpi_nxt (control input) ulpi_stp (control output) usb_clkin u1 u2 u2 u3 u3 u4 u4 u5 u5 electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 37 4.15.1 esdhc timing specifications figure 20 depicts the timing of esdhc, and table 20 lists the esdhc timing characteristics. figure 20. esdhc timing table 20. esdhc interface timing specifications id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 1 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 0 400 khz clock frequency (sd/sdio full speed) f pp 2 2 in normal data transfer mode for sd/sdio card, clock frequency can be any value from 0 to 25 mhz. 040mhz clock frequency (mmc full speed) f pp 3 3 in normal data transfer mode for mmc card, clock frequency can be any value from 0 to 20 mhz. 020mhz clock frequency (identification mode) f od 4 4 in card identification mode, card clock must be 100 khz? 400 khz, voltage ranges from 2.7 to 3.6 v. 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns esdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 esdhc output delay (output valid) t od ?5 5 ns esdhc input / card outputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 esdhc input setup time t isu 5?ns sd8 esdhc input hold time t ih 0?ns sd1 sd3 sd5 sd4 sd7 sdhc_cmd output from esdhc to card sdhc_dat[3:0] sdhc_cmd input from card to esdhc sdhc_dat[3:0] sdhc_clk sd2 sd8 sd6 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 38 4.15.2 esdhc electrical dc characteristics table 21 lists the esdhc electri cal dc characteristics. 4.16 sim timing specifications each sim card interface consist of a total of 12 pins (two separa te ports of six pins each. mostly one port with 5 pins is used ). the interface is meant to be used with synchronous sim cards. this means that the sim module provides a clock for the sim card to use. the frequency of this clock is normally 372 times the data rate on the tx/rx pins, however sim module can work with clk equal to 16 times the data rate on tx/rx pins. there is no timing relationship between the clock and the data. th e clock that the sim module pr ovides to the sim card is used by the sim card to recover the clock from th e data, like a standard uart. all six (or fi ve when a bidirectional txrx is used) of the pins for each half of the sim modul e are asynchronous to each other. there ar e no required timing relationships between the signals in normal mode. however, there ar e some in reset and power down sequences. all sim signals use pad type pad_msr. sim ti ming is fairly relaxed compared to other interfaces and can be met at 50 pf loading with any slew rate setting other than 00. 1 table 21. mmc/sd interface electrical specifications num parameter design value min max unit condition/remark bus signal line load 7 pull-up resistance 47 10 100 k ? internal pu 8 open drain resistance na na na k ? for mmc cards only open drain signal level for mmc cards only 9 output high voltage v dd ? 0.2 v i oh = ?100 a 10 output low voltage 0.3 v i ol =2 ma bus signal levels 11 output high voltage 0.75 x v dd v i oh = ?100 a @v dd min 12 output low voltage 0.125 x v dd v i ol =100 a @v dd min 13 input high voltage 0.625 x v dd v dd + 3 v 14 input low voltage v ss ? 0.3 0.25 x v dd v 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 39 4.16.1 general timing requirements figure 21 shows the timing of the sim module, and table 22 lists the timing parameters. figure 21. sim clock timing diagram 4.16.2 reset sequence 4.16.2.1 cards with internal reset the reset sequence for this kind of sim card is as follows (see figure 22 ): ? after powerup, the clock signal is enabled on sim_clk (time t0) ? after 200 clock cycles, rx must be high. ? the card must send a response on rx acknowledging th e reset between 400 and 40,000 clock cycles after t0. figure 22. internal-reset card reset sequence table 22. sim timing specification?high drive strength num description symbol min max unit 1 sim clock frequency (sim_clk) 1 1 50% duty cycle clock s freq 0.01 5 (some new cards may reach 10) mhz 2 sim_clk rise time 2 2 with c = 50pf s rise ?20ns 3 sim_clk fall time 3 3 with c = 50pf s fall ?20ns 4 sim input transition time (rx, sim_pd) s trans ?25ns sim_clk srise sfall 1/sfreq sim_ven sim_clk sim_rx 2 t0 1 response 2 1 < 200 clock cycles < 40,000 clock cycles 400 clock cycles < mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 40 4.16.2.2 cards with active-low reset the sequence of reset for this ki nd of card is as follows (see figure 23 ): 1. after powerup, the clock signal is enabled on sim_clk (time t0) 2. after 200 clock cycles, rx must be high. 3. sim_rst must remain low for at least 40,000 clock cycles af ter t0 (no response is to be received on rx during those 40,000 clock cycles) 4. sim_rst is set high (time t1) 5. sim_rst must remain high for at leas t 40,000 clock cycles after t1 and a re sponse must be received on rx between 400 and 40,000 clock cycles after t1. figure 23. active-low-reset card reset sequence 4.16.3 power-down sequence power down sequence for sim interface is as follows: 1. sim_pd port detects the removal of the sim card 2. sim_rst goes low 3. sim_clk goes low 4. sim_tx goes low 5. sim_ven goes low each of these steps is completed in one ckil period (usua lly 32 khz). power-down may be started in response to a card-removal detection or la unched by the processor. figure 24 and table 23 show the usual timing requirements for this sequence, with fckil = ckil frequency value. sim_ven sim_clk sim_rx 2 t0 1 response sim_rst t1 1 2 < 200 clock cycles < 40,000 clock cycles 400 clock cycles < 3 3 3 400,000 clock cycles < electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 41 figure 24. smartcard interface power-down ac timing 4.17 ssi timing specifications this section provides the ac timings for th e ssi in master (clocks driven) and slave modes (clocks input). all timings are give n for non-inverted serial clock polarity (ssi_tcr[tsckp] = 0, ss i_rcr[rsckp] = 0) and a n on-inverted frame sync (ssi_tcr[tfsi] = 0, ssi_rcr[rfsi] = 0). if th e polarity of the clock and/ or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (ssi_bclk) and/ or the frame sync (ssi_fs) shown in the figures below. all ssi signals use pad type pad_msr. the following timing specificat ions assume a pad slew rate setting of 11 and a load of 50 pf. when the ssi_mclk output is not used, the maximum ssi b it clock (ssi_bclk) frequency is such that timing can also be met at slew rate settings 10 and 01. 1 table 23. timing requirements for power-down sequence num description symbol min max unit 1 sim reset to sim clock stop s rst2clk 0.9 ? f ckil 0.8 s 2 sim reset to sim tx data low s rst2dat 1.8 ? f ckil 1.2 s 3 sim reset to sim voltage enable low s rst2ven 2.7 ? f ckil 1.8 s 4 sim presence detect to sim reset low s pd2rst 0.9 ? f ckil 25 ns 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. sim_pd sim_rst sim_clk sim__tx sim_ven srst2clk srst2dat srst2ven spd2rst mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 42 table 24. ssi timing ? master modes 1 1 all timings specified with a capacitive load of 25pf. num description symbol min max units notes s1 ssi_mclk cycle time t mclk 15.15 ? ns 2 2 ssi_mclk can be generated from ssi_clkin or a di vided version of the internal system clock (f sys ). s2 ssi_mclk pulse width high / low 45% 55% t mclk s3 ssi_bclk cycle time t bclk 80 ? ns 3 3 ssi_bclk can be derived from ssi_clkin or a di vided version of the internal system clock (f sys ). s4 ssi_bclk pulse width 45% 55% t bclk s5 ssi_bclk to ssi_fs output valid ? 15 ns s6 ssi_bclk to ssi_fs output invalid 0 ? ns s7 ssi_bclk to ssi_txd valid ? 15 ns s8 ssi_bclk to ssi_txd invalid / high impedance 0 ? ns s9 ssi_rxd / ssi_fs input se tup before ssi_bclk 15 ? ns s10 ssi_rxd / ssi_fs input hold after ssi_bclk 0 ? ns table 25. ssi timing ? slave modes 1 1 all timings specified with a capacitive load of 25pf. num description symbol min max units notes s11 ssi_bclk cycle time t bclk 80 ? ns s12 ssi_bclk pulse width high / low 45% 55% t bclk s13 ssi_fs input setup before ssi_bclk 10 ? ns s14 ssi_fs input hold after ssi_bclk 2 ? ns s15 ssi_bclk to ssi_txd / ssi_fs output valid ? 15 ns s16 ssi_bclk to ssi_txd / ssi _fs output invalid / high impedance 0? ns s17 ssi_rxd setup before ssi_bclk 15 ? ns s18 ssi_rxd hold after ssi_bclk 2 ? ns electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 43 figure 25. ssi timing ? master modes figure 26. ssi timing ? slave modes 4.18 12-bit adc specifications table 26. adc parameters 1 characteristic name min typical max unit frequency of operation 200khz ? 12mhz adc clock period t adc 8.33 ? 500 ns low reference voltage v refl v ss ?v refh v high reference voltage v refh v refl ?av dd v integral non-linearity (10% to 90% input signal range) 2 inl ? 3 ? lsb ssi_mclk (output) ssi_bclk (output) ssi_fs (output) ssi_txd ssi_rxd s1 s2 s2 s3 s4 s4 s5 s6 s7 s8 s8 s9 s10 s7 ssi_fs (input) s9 s10 ssi_bclk (input) ssi_fs (input) ssi_txd ssi_rxd s11 s12 s12 s14 s15 s16 s16 s17 s18 s15 s13 ssi_fs (output) s15 s16 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 44 4.19 12-bit dac timing specifications table 27 shows electrical specifications of dac. differential non-linearity (10% to 90% input signal range) 3 dnl ? 0.6 ? lsb monotonicity guaranteed conversion time ? ? 6 t adc cycles sample time ? ? 1 t adc cycles adc power-up time 4 t adpu ??13t adc cycles 5 recovery from auto standby t rec ?0 6t adc cycles input impedance x in ?2k? ? input injection current 6 , per pin i adi ?? 3 ma v refh current i vrefh ?100? na offset voltage internal reference (at the y intercept) v offset0 ?20? lsb offset voltage internal reference (at the 50% fsr point) v offset50 ?12? lsb gain error (transfer path) e gain ?0.2? % spurious free dynamic range sfdr ? 57 ? db signal-to-noise plus distortion sinad ? 55 ? db signal-to-noise ratio snr ? 60 ? db effective number of bits enob ? 9 ? bits 1 all adc parameter measurements are pr eliminary pending full characterization. these measurements were made at v dd =3.3v, v refh = 3.3 v, and v refl = ground. 2 inl measured from v in = 0.1v refh to v in = 0.9v refh 3 inl measured from v in = 0.1v refh to v in = 0.9v refh 4 includes power-up of adc and v ref 5 adc clock cycles 6 the current that can be injected or sourced from an unselect ed adc signal input without impa cting the performance of the adc table 27. dac parameters 1 characteristic name min typical max unit range of digital input words: 497 to 3599 (0x1f1?0xe0f) lsb ? 806 ? uv monotonicity guaranteed conversion time (high-speed) 1 ? ? us conversion time (low-speed) 2 ? ? us conversion rate (high-speed) ? ? 1m conv/sec conversion rate (low-speed) ? ? 500k conv/sec output swing avss + 0.04 ? avdd ? 0.04 v table 26. adc parameters 1 (continued) characteristic name min typical max unit electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 45 4.20 mcpwm timing specifications 4.21 i 2 c timing specifications table 29 lists specifications for the i 2 c input timing parameters shown in figure 27 . table 30 lists specifications for the i 2 c output timing parameters shown in figure 27 . integral non-linearity (497 to 3599) inl ? ? 8.0 lsb differential non-linearity (497 to 3599) dnl ? ? 0.5 lsb gain error (497 to 3599) e gain ? 0.26 ? % effective number of bits enob 9 ? ? bits dac power-up time t dapu ? ? 11 us output load resistance r l 3k ? ? ohm output load capacitance c l ? 400 ? pf power supply ripple rejection psrr ? 60 ? db 1 all measurements were made at v dd = 3.3v, v refh = 3.3v, and v refl = ground table 28. mcpwm timing num characteristic min max unit g1 fb_clk high to output valid ? 7 ns g2 fb_clk high to output invalid 1 ? ns g3 input valid to fb_clk high 3 ? ns g4 fb_clk high to input invalid 1 ? ns table 29. i 2 c input timing specifications between scl and sda num characteristic min max units i1 start condition hold time 2 ? 1/ f sys i2 clock low period 8 ? 1/ f sys i3 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih =2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il =0.5 v) ? 1 ms i6 clock high time 4 ? 1/ f sys i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 ? 1/ f sys i9 stop condition setup time 2 ? 1/ f sys table 27. dac parameters 1 (continued) characteristic name min typical max unit mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 46 figure 27. i 2 c input/output timings 4.22 ethernet assembly timing specifications the following timing specs are defined at the chip i/o pin and must be translated appropriatel y to arrive at timing specs/constraints for th e physical interface. all ethernet signals use pad type pad_fsr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. 1 table 30. i 2 c output timing specifications between scl and sda num characteristic min max units i1 1 1 output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 3 0 . the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the scl low period. the actual position is affected by the prescale and division va lues programmed into the ifdr. however, the numbers given in ta b l e 3 0 are minimum values. start condition hold time 6 ? 1/ f sys i2 1 clock low period 10 ? 1/ f sys i3 2 2 because i2c_scl and i2c_sda are open-collector-type ou tputs, which the processor can only actively drive low, the time i2c_scl or i2c_sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih =2.4 v) ? ? s i4 1 data hold time 7 ? 1/ f sys i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 3 ns i6 1 clock high time 10 ? 1/ f sys i7 1 data setup time 2 ? 1/ f sys i8 1 start condition setup time (for repeated start condition only) 20 ? 1/ f sys i9 1 stop condition setup time 10 ? 1/ f sys 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. i2 i6 i1 i4 i7 i8 i9 i5 i3 i2c_scl i2c_sda electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 47 4.22.1 receive signal timing specifications the following timing specs meet the re quirements for mii and rmii interface s for a range of transceiver devices. figure 28. mii/rmii receive signal timing diagram 4.22.2 transmit signal timing specifications table 31. receive signal timing num characteristic mii mode rmii mode unit min max min max ? rxclk frequency ? 25 ? 50 mhz e1 rxd[n:0], rxdv, rxer to rxclk setup 1 1 in mii mode, n = 3; in rmii mode, n = 1 5?4? ns e2 rxclk to rxd[n:0], rxdv, rxer hold 1 5?2? ns e3 rxclk pulse width high 35% 65% 35% 65% rxclk period e4 rxclk pulse width low 35% 65% 35% 65% rxclk period table 32. transmit signal timing num characteristic mii mode rmii mode unit min max min max ? txclk frequency ? 25 ? 50 mhz e5 txclk to txd[n:0], txen, txer invalid 1 1 in mii mode, n = 3; in rmii mode, n = 1 4?5? ns e6 txclk to txd[n:0 ], txen, txer valid 1 ? 25 ? 14 ns e7 txclk pulse width high 35% 65% 35% 65% t txclk e8 txclk pulse width low 35% 65% 35% 65% t txclk valid data rxclk (mii) / extal (rmii) rxd[n:0] rxdv, rxer e3 e4 e1 e2 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 48 figure 29. mii/rmii transmit signal timing diagram 4.22.3 asynchronous input signal timing specifications figure 30. mii/rmii async inputs timing diagram 4.22.4 mdio serial management timing specifications table 33. mii/rmii transmit signal timing num characteristic min max unit e9 crs, col minimum pulse width 1.5 ? txclk period table 34. mdio serial management channel signal timing num characteristic symbol min max unit e10 mdc cycle time t mdc 400 ? ns e11 mdc pulse width 40 60 % t mdc e12 mdc to mdio output valid ? 375 ns e13 mdc to mdio output invalid 25 ? ns e14 mdio input to mdc setup 10 ? ns e15 mdio input to mdc hold 0 ? ns valid data txclk (mii) / extal (rmii) txd[n:0] txen, txer e7 e8 e5 e6 crs, col e9 electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 49 figure 31. mdio serial management channel timing diagram 4.23 32-bit timer module timing specifications table 35 lists timer module ac timings. 4.24 dspi timing specifications the dma serial peripheral interface (dspi) provides a synchronou s serial bus with master and slave operations. many of the transfer attributes are programmable. table 36 provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the mcf54418 reference manual for information on the modified tran sfer formats used for communicating with slower peripheral devices. all dspi signals use pad type pad_msr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. 1 table 35. timer module ac timing specifications name characteristic min max unit t1 dt n in cycle time ( n =0:3) 3 ? 1/ f sys/2 t2 dt n in pulse width ( n =0:3) 1 ? 1/ f sys/2 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. table 36. dspi module ac timing specifications 1 name characteristic symbol min max unit notes master mode ? dspi_sck frequency f sck ?50mhz ds1 dspi_sck cycle time t sck 20 ? ns 2 ds2 dspi_sck duty cycle ? (t sck ?? 2) ? 2.0 (t sck ?? 2) + 2.0 ns 3 ds3 dspi_pcs n to dspi_sck delay t csc (t sck ?? 2) ? 2.0 ? ns 4 ds4 dspi_sck to dspi_pcs n delay t asc (t sck ?? 2) ? 3.0 ? ns 5 ds5 dspi_sck to dspi_sout valid ? ? 5 ns mdc (output) e11 mdio (output) mdio (input) e11 e12 e13 valid data e14 e15 valid data e10 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 50 ds6 dspi_sck to dspi_sout invalid ? ?5 ? ns ds7 dspi_sin to dspi_sck input setup ? 6 ? ns ds8 dspi_sck to dspi_sin input hold ? 0 ? ns slave mode ? dspi_sck frequency f sck ?f sys ? 8mhz ds9 dspi_sck cycle time t sck 8 ?? f sys ?ns ds10 dspi_sck duty cycle ? (t sck ?? 2) ? 2.0 (t sck ?? 2) + 2.0 ns ds11 dspi_sck to dspi_sout valid ? ? 12 ns ds12 dspi_sck to dspi_sout invalid ? 0 ? ns ds13 dspi_sin to dspi_sck input setup ? 2 ? ns ds14 dspi_sck to dspi_sin input hold ? 7 ? ns ds15 dspi_ss active to dspi_sout driven ? ? 10 ns ds16 dspi_ss inactive to dspi_sout not driven ? ? 10 ns 1 timings shown are for dmcr[mtfe] = 0 (classic spi) and dctar n [cpha] = 0. data is sampled on the dspi_sin pin on the odd-numbered dspi_sck edges and driven on the dspi_sout pin on even-numbered dspi edges. 2 when in master mode, the baud rate is programmable in dctar n [dbr], dctar n [pbr], and dctar n [br]. 3 this specification assu mes a 50/50 duty cycle setting. the duty cycle is programmable in dctar n [dbr], dctar n [cpha], and dctar n [pbr]. 4 the dspi_pcs n to dspi_sck delay is programmable in dctar n [pcssck] and dctar n [cssck]. 5 the dspi_sck to dspi_pcs n delay is programmable in dctar n [pasc] and dctar n [asc]. table 36. dspi module ac timing specifications 1 (continued) name characteristic symbol min max unit notes electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 51 figure 32. dspi classic spi timing ? master mode figure 33. dspi classic spi timing ? slave mode dspi_pcs n dspi_sck dspi_sout dspi_sin dspi_sck (dctarn[cpol] = 1) (dctarn[cpol] = 0) data last data first data first data data last data ds1 ds2 ds2 ds3 ds4 ds6 ds5 ds7 ds8 dspi_ss dspi_sck dspi_sout dspi_sin dspi_sck (dctarn[cpol] = 1) (dctarn[cpol] = 0) last data first data data data first data last data ds9 ds10 ds10 ds11 ds12 ds13 ds14 ds15 ds16 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 52 4.25 sbf timing specifications the serial boot facility (sbf) provides a m eans to read configuration information and system boot code from a broad array of spi-compatible eeproms, flashes, frams, nvsrams, etc. table 37 provides the ac timing specifications for the sbf. all sbf signals use pad type pad_msr. the following timing specifi cations assume a pad slew rate setting of 11 and a load of 50 pf. 1 figure 34. sbf timing 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. table 37. sbf ac timing specifications name characteristic symbol min max unit notes ? sbf_ck frequency f sbfck ? 62.5 mhz sb1 sbf_ck cycle time t sbfck 16.67 ? ns 1 1 at reset, the sbf_ck cycle time is t ref ? 60. the first byte of data read from t he serial memory contains a divider value that is used to set the sbf _ck cycle time for the duration of the serial boot process. sb2 sbf_ck high/low time ? 30% ? t sbfck sb3 sbf_cs to sbf_ck delay ? t sbfck ? 2.0 ? ns sb4 sbf_ck to sbf_cs delay ? t sbfck ? 2.0 ? ns sb5 sbf_ck to sbf_do valid ? ? 5 ns sb6 sbf_ck to sbf_do invalid ? ?5 ? ns sb7 sbf_di to sbf_sck input setup ? 10 ? ns sb8 sbf_ck to sbf_d i input hold ? 0 ? ns sbf_cs sbf_do sbf_di data last data first data first data data last data sb3 sb4 sb6 sb5 sbf_ck sb1 sb2 sb2 sb7 sb8 electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 53 4.26 1-wire timing specifications specifications for the 1-wire interface are provided by maxim in tegrated products, inc. please re fer to data sheet information for the appropriate device at www.maxim-ic.com. 4.27 general purpose i/o timing specifications figure 35. gpio timing 4.28 rapid general purpose i/o timing specifications rgpio signals use a mix of pad types: pad_fsr, pad_msr, and pad_ssr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. table 38. gpio timing 1 1 these general purpose specifications apply to the following signals: irq n , all uart signals, all timer signals, flexcan signals, dack n and dreq n , and all signals configured as gpio. num characteristic min max unit g1 fb_clk high to gpio output valid ? 9 ns g2 fb_clk high to gpio output invalid 1 ? ns g3 gpio input valid to fb_clk high 9 ? ns g4 fb_clk high to gpio input invalid 1.5 ? ns table 39. rgpio timing num characteristic min max unit rg1 pst_clk high to rgpio output valid ? 6 ns rg2 pst_clk high to rgpio output invalid 0.5 ? ns rg3 rgpio input valid to pst_clk high 6 ? ns rg4 pst_clk high to rgpio input invalid 1.5 ? ns g1 fb_clk gpio outputs g2 g3 g4 gpio inputs mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 54 figure 36. rgpio timing 4.29 jtag and boundary scan timing specifications all jtag signals use pad type pad_msr except for tclk which use pad type pad_fsr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. 1 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. table 40. jtag and boundary scan timing num characteristics 1 1 jtag_en is expected to be a static signal. henc e, specific timing is not associated with it. min max unit j1 tclk frequency of operation dc 25 mhz j2 tclk cycle period 40 ? ns j3 tclk clock pulse width 20 ? ns j4 tclk rise and fall times ? 3 ns j5 boundary scan input data setup time to tclk rise 4 ? ns j6 boundary scan input data hold time after tclk rise 20 ? ns j7 tclk low to boundary scan output data valid ? 13 ns j8 tclk low to boundary scan output high-z ? 13 ns j9 tms, tdi input data setup time to tclk rise 4 ? ns j10 tms, tdi input data hold time after tclk rise 10 ? ns j11 tclk low to tdo data valid ? 12 ns j12 tclk low to tdo high-z ? 0 ns j13 trst assert time 32 ? ns j14 trst setup time (negation) to tclk high 8 ? ns rg1 pst_clk rgpio outputs rgpio inputs rg2 rg3 rg4 electrical characteristics mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 55 figure 37. test clock input timing figure 38. boundary scan (jtag) timing figure 39. test access port timing figure 40. trst timing tclk v il v ih j4 j4 (input) j2 j3 j3 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j7 j8 j7 j6 j5 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst j13 j14 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice electrical characteristics freescale semiconductor 56 4.30 debug ac timing specifications table 41 lists specifications for the debug ac timing parameters shown in figure 41 and table 42 . all debug signals use pad type pad_msr except for pstclk whic h use pad type pad_fsr. the following timing specifications assume a pad slew rate setting of 11 and a load of 50 pf. 1 figure 41. real-time trace ac timing figure 42. bdm seri al port ac timing 1.these timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). when operating this interface at lo wer frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing emi. table 41. debug ac timing specification num characteristic min max units d0 pstclk cycle time 0.5 0.5 1/ f sys d1 pstclk rising to pstddata valid ? 3.0 ns d2 pstclk rising to pstddata invalid 0.5 ? ns d3 dsi-to-dsclk setup 1 ? pstclk d4 1 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of pstclk. dsclk-to-dso hold 4 ? pstclk d5 dsclk cycle time 5 ? pstclk d6 bkpt assertion time 1 ? pstclk pstclk pstddata[7:0] d0 d1 d2 past current dsclk dsi dso next current d5 d3 d4 package information mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 57 5 package information the latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire . table 42 lists the case outline numbers per device. use these numbers in the web page?s keyword search engine to find the latest package outline drawings. 6 product documentation documentation is available from a local freescale distributor, a freescale sales office, the fr eescale literature distribution center, or through the freescal e world-wide web address at http://www.freescale.com/coldfire . table 42. package information device package type case outline numbers mcf54410 196 mapbga 98arh98217a mcf54415 256 mapbga 98arh98219a mcf54416 mcf54417 mcf54418 mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice revision history freescale semiconductor 58 7 revision history table 43 summarizes revisions to this document. table 43. revision history rev. no. date summary of changes 2 10 jun 2009 in section 2.2, ?supply voltage sequencing ? added the following note: note all i/o vdd pins must be powered on when the device is functioning, except when in standby mode. in standby mode, all i/o vdd pins, except vstby_rtc (battery), can be switched off. added section 3.2, ?pinout?169 mapbga ? and section 3.3, ?pinout?256 mapbga ? and updated ta b l e 5 with pin locations. in section 4.1, ?absolute maximum ratings ?: ? added usb otg, usb host, adc, dac/adc, and rtc standby supply voltages in section 4.5, ?dc electrical specifications ?: ? added rtc standby supply voltage ? split out power supplies and i/o characteristics to two separate tables in section 4.10, ?flexbus timing specifications ?: ? changed maximum frequency to 100mhz and updated specs throughout the table ? changed fb2 maximum from 5 to 6 ? added notes to figure 11 and figure 12 in section 4.12, ?ddr sdram cont roller timing specifications ?: ? changed minimum frequency from 50 to 100 ? changed maximum dd1 from 20 to 10 ? changed dd5 from 2 to 0.5 x t sdck ? 1 ? changed dd6 from 1.2 x t sdck to wl + 0.2 x t sdck ? changed dd7 from 1.5 to 0.7 ? changed dd8 from 1.0 to 0.7 ? changed dd9 from 1.0 to 0.5 ? changed dd10 from 0.25 x t sdck + 0.5 to 0.375 x t sdck in section 4.17, ?ssi timing specifications ?: ? changed s7, s9, s15, and s17 from 10 to 15 in section 4.22.2, ?transmit signal timing specifications ?: ? changed e5 for mii from 5 to 4 in section 4.20, ?mcpwm timing specifications ?: ? changed g2 from 2 to 1 in section 4.24, ?dspi timing specifications ?: ? changed ds3 from (2 x 1/fsys) ? 2.0 to (t sck 3 2) ? 2.0 ? changed ds4 from (2 x 1/fsys) ? 3.0 to (t sck 3 2) ? 3.0 ? changed ds7 from 7 to 6 ? changed ds11 from 4 to 12 in section 4.25, ?sbf timing specifications ?: ? changed sb5 maximum from 5 to 3 ? changed sb6 minimum from ?5 to 5 in section 4.26, ?1-wire timing specifications ?: ? added link to 1-wire specs in section 4.27, ?general purpose i/o timing specifications ?: ? changed g2 from 1.5 to 1 in section 4.28, ?rapid general pur pose i/o timing specifications ?: ? changed rg1 from 3 to 6 ? changed rg2 from 1.5 to 0.5 ? changed rg3 from 3 to 6 in section 4.29, ?jtag and boundary scan timing specifications ?: ? changed j9-12 and j14 from tbd in section 4.30, ?debug ac timing specifications ?: ? changed d2 from 1.5 to 0.5 revision history mcf5441x coldfire ? microprocessor data sheet, rev. 6 preliminary?subject to change without notice freescale semiconductor 59 3 31 july 2009 changed 169mapbga package to 196mapbga throughout. mcf54410 device now supports a single ssi module and one ethernet controller with ieee 1588 support 4 17 aug 2009 updated mcf5441 x signal information and muxing table with 196mapbga pin locations changed sd_d n pin locations on 256 mapbga package added note to section 4.6, ?output pad loading and slew rate ? 5 29 jan 2010 added orderable part numbers 6 swapped locations of rtc_extal and rtc_xtal pins in ta b l e 5 , figure 7 , and figure 8 corrected instances of mcf5445 x to mcf5441 x added thermal characteristics to ta bl e 7 added case outline numbers to ta b l e 4 2 changed pll supply voltage from ??0.5 to +2.0? to ??0.3 to +4.0? in ta bl e 6 miscellaneous corrections based on information from shared review comments by team members table 43. revision history (continued) rev. no. date summary of changes document number: mcf54418 rev. 6 09/2010 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2010. all rights reserved. preliminary?subject to change without notice |
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